Protocol Mapping for a Bus-Based COMA Multiprocessor

As microprocessors become faster and demand more bandwidth the already limited scalability of a shared-bus decreases even further. Cache only memory architecture (COMA) for distributed shared memory multiprocessors has a potential to effectively decrease the gap between high performance microprocessors and bus. The concept of COMA is organizing traditional main memory as a large cache. COMA allows a multiprocessor to adapt quickly to dynamic memory access pattern of application programs and thereby the processors utilize the memory local to each processing node better, resulting shorter memory access latency and less bandwidth demand on the system bus. However, organizing memory as a cache not only requires additional physical memory but also complicates cache coherence protocol due to the need of relocating memory blocks for replacement. In this paper we demonstrate how cache coherence protocol for COMA can be efficiently implemented on a shared bus. Especially, we present a scheme that allows relocating memory blocks to be done in a single bus transaction.